The present invention relates to ferroelectric memories, and more particularly to improving the data retention of a 2T/2C memory device.
Referring now to FIG. 1, a 1T/1C (One Transistor, One Capacitor) memory cell 100 is shown. As is known in the art, memory cell 100 includes a transistor 102 having a gate coupled to a word line node WL and a source/drain coupled to a bit line node BL. Another source/drain of transistor 102 is coupled to ferroelectric capacitor 104, which in turn is coupled to a plate line node PL.
Referring now to FIG. 2, a 2T/2C (Two Transistor, Two Capacitor) memory cell 200 is shown. As is known in the art, memory cell 200 includes a first transistor 202 having a gate coupled to a first word line node WL1 and a source/drain coupled to a first bit line node BL1. Another source/drain of transistor 202 is coupled to a first ferroelectric capacitor 204, which in turn is coupled to a plate line node PL. Memory cell 200 also includes a second transistor 206 having a gate coupled to a second word line node WL2 and a source/drain coupled to a second bit line node BL2. Another source/drain of transistor 206 is coupled to a second ferroelectric capacitor 208, which in turn is coupled to the plate line node PL.
Referring now to FIG. 3, a hysteresis loop associated with a ferroelectric capacitor of a memory cell is shown. The hysteresis loop is produced by plotting polarization versus applied voltage. In FIG. 3, the P polarization term is defined as the change in polarization from a negative remanent polarization (point A in the hysteresis loop) to a positive voltage induced polarization (point B in the hysteresis loop) and the U polarization term is defined as the change in polarization from a positive remanent polarization (point C in the hysteresis loop) to a positive voltage induced polarization (point B in the hysteresis loop). Note that the P term is greater than the U term. There are actually four polarization terms: Pss (P same state, which is defined as a P term measured from a ferroelectric capacitor imprinted at a negative remanent polarization state), Pos (P opposite state, which is defined as a P term measured from a ferroelectric capacitor imprinted at a positive remanent polarization state), Uss (U same state, which is defined as a U term measured from a ferroelectric capacitor imprinted at a positive remanent polarization state), and Uos (U opposite state, which is defined as a U term measured from a ferroelectric capacitor imprinted at a negative remanent polarization state). (Psw)os is defined as Pos−Uos.
The “second half time effect” is shown in FIG. 4. The P term (Pos=P opposite state) and U term (Uss=U same state) are plotted versus baking time in years. It can be clearly shown in FIG. 4 that most of the reduction in the P term occurs in the first ten years, and only a small portion of the reduction in the P term occurs in the next ten years. The following observations can be made regarding FIG. 4: Pos=40−1*In(t), wherein t is time in hours. Note that time is given in hours in the graph of FIG. 4, wherein 8760 hours equals one year and 87600 hours equals ten years. Both notations are added in the plot. When t=87600 hours or ten years Pos=28.6 μC/cm2; when t=twenty years, Pos=27.9 μC/cm2. During the first ten years, there is a 28.5% reduction in the Pos term and during the second ten years there is only a 1.75% reduction.
Referring now to the table shown in FIG. 5, certain observations, assumptions, and conclusions can be made regarding the performance of a 2T/2C memory cell. The Pss and Uss are constant terms during imprint because the polarity of internal bias is parallel to that of polarization. Imprint recovery takes at least the same amount of time as imprint at the same temperature, because imprint and imprint recovery both are controlled by the same charged defects migration mechanism. ΔPos=−ΔUos based on capacitor level data, because the decrease in Pos is due to the relaxation back switching. The back switched portion of P is the source of increase in Uos. The Pos, Uos, and (Psw)os (=Pos−Uos) terms are linear functions of logarithmic time. The charge equation for the Pos term is Pos=40−1*In(t), wherein t is time in hours. The charge equation for the Uos term is Uos=20+1*In(t), wherein t is time in hours. The charge equation for (Psw)os is (Psw)os=20−2*In(t), wherein t is time in hours. The rate for (Psw)os is 10%, which means that it is not an appropriate material for a ferroelectric memory. At 10 years, (Psw)os=−2.76 μC/cm2. This material has no ten year retention if used as 2T/2C ferroelectric memory without the enhancement in the present invention.
The conventional performance of a 2T/2C ferroelectric memory cell is described in further detail below with respect to FIG. 6. If parts are imprinted as a conventional 2T/2C memory cell during production as screening, the lifetime of parts is shortened due to opposite state margin degradation. This is clearly shown in FIG. 6. Note that the data margin for opposite state charge terms is zero at about two years. For materials in this case study, the opposite state retention of parts is only 1808 hours (0.2 year) assuming a minimal sense margin of 5 μC/cm2. After ten years the opposite state margin is actually negative.
FIG. 6 illustrates the conventional screening process that imprints the capacitors A and B. The retention lifetimes are shortened due to the fact that both of the capacitors contribute to the degradation. Pos from capacitor A is lower and Uos from capacitor B is higher. Thus, the signal margin of a 2T/2C (Psw)os is largely reduced and the retention lifetime is shortened. The table of FIG. 6 defines the relationship between the external data “0” and “1” and the internal polarization terms of capacitor A and B. For example, the P term from capacitor A and the U term from capacitor B is the signal margin of an external data “0”. Then the margin for a data “1” is the P term from capacitor B and the U term from capacitor A. The definitions of “1” and “0” are interchangeable. When P−U>5 μC/cm2, the part works properly. When P−U<5 μC/cm2, the part fails. FIG. 6 describes the case that Pss−Uss is always 20 μC/cm2, and thus the part never fails data “0”. However, Pos−Uos=5 μC/cm2 at 1808 hours, thus the retention life is only 1808 hour for data “1”.
What is desired, therefore, is a method for improving data retention in a 2T/2C ferroelectric memory beyond the time limits on the order shown in FIG. 6.